I have been working my way through AN58726 and more specifically the second example.

When building the project it seems to throw an error on the code added in the main.c file.

      USB_IN_Keyboard_Data, 8);
      /* Loads IN data for Volume Controller */
      USBFS_1_LoadInEP(2, USB_IN_Volume_Data, 1);

Build error: 'USB_IN_Keyboard_Data' undeclared (first use in this function)

Build error: 'USB_IN_Volume_Data' undeclared (first use in this function)

My assumption is that they are not defined in the new project.h but that is just a first guess.

Let me know what you think. I have zipped up the project and attached it here.

Randy

I have configured the three RX basic mailbox for which I am assigning the CAN ID (Extended ID)through code and trying to capture the data coming with these  IDs in the CAN interrupt(CAN_ReceiveMsg()). It is storing some unknown data which is not at all on the bus. Also, observation is the IDs of the mailbox is getting change sometimes. Different from the ID which has been set through the code. It is taking some other CAN ID which CAN is receiving periodically on the bus.

Why it is storing unknown/junk data which is not at all on the bus from the desired basic mailbox ? 

Is basic Rx mailbox can change it's ID by its own based on the messages coming on the bus?

Is using three basic mailbox is good way of design to capture data with three different extended CAN IDs and capturing data with these three IDs using ID filter in the interrupt?

Please respond.

regards,

Aditya

Hi there, 

I got problem with interfacing Cypress SPI Master running on PSOC 5 Cortex-M3 MCU with Avalon-ST SPI Core running on MAX 10 FPGA Altera. 

Any Suggests, 

I have a launcher-only dual-image bootloader and a combination application that it boots.  Within the combination application, I attempt to change the active image using Bootloadable_SetActiveApplication() call. The call fails. I traced the problem all the way to an SPC call failing within CySpcLoadRowFull(). I think the root of the problem is that SPC is not started, so calling CySpcStart() fixes the problem. I also tried calling CyFlash_Start() instead, but that one seems to hang in the while() loop.

There is no mention of having to do something to initialize flash anywhere in the Bootloader/Bootloadable documentation. As a matter of fact, the CySpcStart() call is barely mentioned at all when I search the website.  I am using PSoC Creator 4.1 - did something change with regards to this?

Anyway, I have a workaround, but I think this needs clarification and at least a documentation change.

Hello everyone
By reference to the first generation of PSoC (PSoC 1),the analog input range is 0-5 volt with AGND equal to 2.5v if Ref Mux=(Vdd/2)+/-(Vdd/2).
by using psoc 5lp , the range is [0-1.020]v or [0-4.080]v ???
also vref =1.020 as default, why that ?why my analog input shouldn't exceeded 4.080 v?
the range in psoc 1 is better than psoc 5,right ?

What is the equivalent of AGND in psoc 5lp ???This is a question in need of an answer.
the problem is :
i worked on psoc1 cy8c29466 with range 0-5 v and agnd=2.5 , i have implemented a big project using it and It works well, i want to development it by using psoc5lp cy8c5888 ,But there is a difference in input voltage range ,and AGND ??
please help

I have attached image about my project using PSoC1
Thanks in advance

Hello Every one,

I am trying to communicated two PSoC boards (5LP) using bidirectional spi communication but it is not working. I do not know why I am enabling and disabling the TR and RX side correctly. 

I have not found any example project on the internet where i can get some help.

I would be very thankful to you if any body can share some example project that can help me.

Looking forward for your answer.

Regards

Hello everyone,

I'm using PSoC 5LP(CY8C586LTI-LP038) with PSoC Creator version 3.3.

Iam trying to capture the PWM from Futaba R617FS. As of now only one channel is connected as input to the PSoC.

The timer with period 16.043 ms is used. Trigger mode is Rising edge, capture mode is Falling edge,interrupt is enabled only on the Terminal Count. ISR will Send Character 'A' , whenever it is raised.

Pin_2 is been used to monitor the output.

The questions are:

1. In the attached project "Timer_1" configuration, how the Reset functionality works? I have followed the explanation provided in data sheet but not able to find the solution.

2. Irrespective of the Channel 1 input Terminal count interrupt should be raised or not ?

3. The APIs  as given in the attached project Timer_1_STATUS, and Timer_1_EnableTrigger(), how are they functioning in the attached project?

please provide explanations for the same.

Thank you in advance. 

Hi.

In my design I've defined an 8 pin non contiguous output port.

After executing Build, there is no API created for the port.

I can't post the design here.

Is there a solution for this?

Also, in the same design I have a 4 pin non contiguous input port. For this port there is only one file in the API - Port_aliases.h. There are no Read() or Write() functions for the pins. How can I read these pins?

Thanks.

Hello Every body,

I am doing SPI communication between Pi and PSOC 5LP.

I placed a command

while(!(SPIS_ReadTxStatus() & SPIS_STS_SPI_DONE));

But by doing this, my program just takes too long to fulfill the condition and when I replace the above condition with just:

while(!(SPIS_STS_SPI_DONE));

It does not!

I wonder why it is behaving so wierd?

Looking forward to your answers!

Hello everyone,

I was just trying work on Timers. I'm using Psoc5lp(CY8C5868LTI-038). I have checked the data sheet still doubt is not clarified.
What input should be given to the "Reset" input terminal. Please provide more information.

Thanks in advance.

Hi everyone,
I am working with PSoC5LP in which i should command 3 PWM blocks with a clock of 150MHz.
The problem is that even if i put 150 MHz as the frequency i wanna into the clock block,
when i measure the output frequency, it is 24 MHz that is the Master Clock frequency (the MCLK is the parent clock of my 150 MHz).
If I change the master clock parameter, also the output measured clock changes.
Am i wrong on trying to get 150 MHz from 24?
With PsoC 5LP is there a way to get a 150 MHz clock?

Hi all,

Working with a fresh install of Designer 5.4 SP1.

When attempting to build the following errors are thrown:

name translation failed on C:/Program\ Files\ (x86)/Cypress/PSOCDE~1/5.4/Common/CYPRES~1 - 3
name translation failed on C:\Program - 2
name translation failed on Files - 2
name translation failed on (x86)\Cypress\PSOCDE~1\5.4\Common\CYPRES~1\tools\include\CY8C22~2 - 3
make: *** No rule to make target `C:\PSoC', needed by `lib/obj/i2chwcommon.o'.  Stop.
 
B4347c1 - 1 error(s) 0 warning(s) 08:54:30

I attempted one 'fix' by following the directions at the bottom of the thread found here, but the error still persists after the reinstall.

This project was created on an 'old' workstation that has been replaced, the project was copied over to this new workstation without being modified in any way.

Any ideas?

Hi,

I want to make use of entire Port1 of CY8KIT-059 (PSoc5 stick). Unfortunately, Pins 1.0, 1.1 and 1.3 are taken by JTAG and not assignable (screenshot attached). Is there any way to reclaim those pins? Are they become available if using Miniprog3?

ANKS just posted on another thread that PSOC 5 was obsolete.

Can we do a lifetime buy?  How would I arrange that?

Hello every one, I am doing a project about MQTT  protocol and w5100. please help me!

I have encountered an issue where the value from the precious channel affects the next value in the Sequencing SAR ADC. It appears that the settling time after the mux has changed the input, has a longer settling time than the time before the next ADC sample.

My settings: The clock range is set to be between 1-18MHz and the issue exists over the entire range but is lager closer to 18MHz. I'm using external Vref (2.5V reference voltage), "0.0 to 2.048 (Single Ended) 0 to Vref*2", internal clk, hardware trigger (from pwm).

How to replicate: add a SAR seq object, connect some channels (IOs) and set the voltage to high, low low low (from the bottom). Check the result. I get some thing like 1000-60-4-0 (should be 1000 - 0 - 0 -0) about 6% of the previous value is added to the next.

Also, I read that the Vrefhi-out is the ground reference and when looking at the Analog routing it looks like it is going from the SAR into the SAR. Not much in the documentation regarding this critical signal. I assume one would like to connect it to AGND. It can be done in the analog routing, but I assume there is an API for this. I can't be the only one wanting to ground the negative input to the ADC.

/Jacob

Hi,

I'm doing CapSense proximity sensing. Since I need information about the distance, I work with the sensor raw data. This works well. The only disadvantage is that the the raw data has some noise on it (if necessary, I can provide data). To get rid off the noise, I use the DFT block to process the CapSense raw data values. However, it seems that it's hard to setup the DFB the right way.

On a first thought, I think I need something like a FFT on the data, with only the DC bin as returned value. Is a FFT possible with the DFB? If not, how can I figure out how to setup the DFB to clean the noise out of the signal?

Regards,

Ralf

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