Hello,
Our project needs an external power supply of 5V given to the psoc 5lp Kit by a DC DC converter.
we would need to connect a MICROUSB cable from a laptop to the kit in order to use a USBuart for communication.
is there anything to modify or to add in order not to give a double Power Supply to the kit when both the external power supply and the microusb are connected to the system?
thank you
S&D
Hello community
I have psoc 5lp and creator 4.0.
Could you tell me the steps to implement in File spi mode.
I did the instructive and did not get results.
Hi, I'm running into some trouble with power consumption and I'm wondering if this seems like a design problem. Here's the situation:
I have a dozen copies of a custom PCBA from a well established assembly house
I have an empty project with a single pin assigned to 12.6, and the following code:
pin_SetDriveMode(pin_DM_DIG_HIZ);
CyDelay(10);
CyPmSaveClocks();
CyPmHibernate();
I expect this design to draw around a microamp in sleep, but two instances of the board fail to do that. They start out drawing 0.4 mA and slowly creep up over a period of about a minute until they're drawing 4 mA. Toggling the reset line resets the cycle. All the other boards draw less than a uA.
I discovered that if I set the drive mode to ALG_HIZ, these boards fall into line (although I do need PICU interrupts on this particular pin). There's a 200 kOhm pulldown on 12.6, and shorting the pin to ground or VDDD doesn't have any effect.
Any ideas what could be causing this? DFM things to check? Thanks in advance!
We are using the EMIF and try to check the connection via several test sequences. With the 8-bit macros (SET, GET) we get the correct values returned, although the memory window only shows the values on even addresses. The odd addresses display always 0x00 all over the 64 k of the external SRAM (starting from 0x60000000).
Are the displayed values correct? And does it mean I place (SET) my "odd-test-byte" somewhere else and I read (GET) it back from that wrong location?
Or does the memory window always expects a 16 bit SRAM, and therefore doesn't display the odd values?
Hi, I'm new here.
I'm trying to establish I2C communication between my PSOC 5LP (as master) and one attiny85 (as slave) that is sending one float. I programmed attiny with arduino (library TinyWireS.h) and I want to know if it is possible to read the value via PSOC.
Master code:
#include <project.h>
#define SLAVE_ADDR 0x26
union v{
float val;
char8 data[5];
} temp;
volatile uint8 status;
uint8 i;
int main()
{
CyGlobalIntEnable; /* Enable global interrupts. */
LCD_Start();
LCD_Position(0,1);
LCD_PrintString("Temp: ");
I2C_1_Start();
status = I2C_1_MasterSendStart(SLAVE_ADDR, I2C_1_READ_XFER_MODE);
if (status == I2C_1_MSTR_NO_ERROR){
CyDelay(1);
for (i=0; i<5; i++){
if(i < 4) {
temp.data[i] = I2C_1_MasterReadByte(I2C_1_ACK_DATA);
}
else temp.data[i] = I2C_1_MasterReadByte(I2C_1_NAK_DATA);
}
LCD_Position(1,1);
LCD_PrintNumber(temp.val);
}
I2C_1_MasterSendStop();
I2C_1_MasterClearReadBuf();
}
slave code:
#include <TinyWireS.h>
#include <OneWire.h>
#include <DallasTemperature.h>
#define SLAVE_ADDR 0x26
#define ONE_WIRE_BUS 4
OneWire oneWire(ONE_WIRE_BUS);
DallasTemperature sensors(&oneWire);
void setup()
{
sensors.begin();
TinyWireS.begin(SLAVE_ADDR);
TinyWireS.onRequest(requestEvent);
}
union v{
float val;
unsigned char data[4];
} t1, t2;
void loop()
{
}
void requestEvent()
{
//sensors.requestTemperatures();
t1.val = 123.45;
TinyWireS.send (t1.data[reg_position]);
}
Hi
I am trying to build a simple SPI module with verilog. I simply created a verilog module for this. I designed a block with clock input, clock output and data output.
My verilog codes are as follows.
`include "cypress.v"
module ParalelToSerial (
output CLKOUT,
output DOUT,
input CLKIN
);
//`#start body` -- edit after this line, do not edit this line
reg clk_count;
reg dout;
reg clkout;
reg [7:0] status;
reg [7:0] control_reg_out;
cy_psoc3_control #(.cy_init_value (8'b00000000), .cy_force_order(`TRUE)) //Default mode
MyTxReg(.control(control_reg_out));
cy_psoc3_control #(.cy_init_value (8'b00000000), .cy_force_order(`TRUE)) //Default mode
MyStatus(.control(status));
always @ (posedge CLKIN)
beginif(status==1'b1)
begin
clkout = 0;
dout=control_reg_out[clk_count];
clkout = 1;
clk_count = clk_count + 1;
if(clk_count == 8)
begin
status = 0;
clk_count=0;
end
end
else
begin
clk_count=0;
dout=0;
clkout=0;
end
end
assign DOUT = dout;
assign CLKOUT = clkout;
//`#end` -- edit above this line, do not edit this line
endmodule
//`#start footer` -- edit after this line, do not edit this line
//`#end` -- edit above this line, do not edit this lin
This codes not working. I must be making a mistake.
In main.c I send data to verilog with CY_SET_REG8 command.
exactly as below
CY_SET_REG8(ParalelToSerial_1_MyTxReg__CONTROL_REG,0x81);
CY_SET_REG8(ParalelToSerial_1_MyStatus__CONTROL_REG,0x01);
What I would like to do is, if the status variable is 0x01, I want to send the 8 bit data in My TxReg as serial. It is very important for me to do this if I can do this I will increase the number of channels.
How can I solve this problem? Where do I make mistakes
What's the difference between 'DMA request' and 'polled' configuration of Filter component? I've seen example projects Filter_ADC_VDAC and Filter_ADC_VDAC_poll but I still don't know.
Actually, I don't know what means 'polled'?
I'm new into this.
Thanks in advance
Hi, can someone please upload 'VoltageDisplay_DelSigADC' project? It's an example project for cy8ckit-050, but I can't find it in 'Find example project' with my cy8ckit-059.
Thank you very much in advance
Hi Experts
only MDIO slave/device is supported, right ?
How about MDIO master?
Appreciate you answers.
Hi friends,
Looking forward your support to select a suitable MCU with capsense in PSOC/PROC,
Requirements are,
1. minimum 6 capsense I/O's
2. minimum 10 digital I/O's excluding capsense I/O's
3. UART communication interface to communicate with external device.
4. minimum 2 PWM output required
with Thanks & Regards,
K Jagatheeswaran
Is it a good solution, or a bad idea, to use 20-bit delta-sigma ADC (PSoC 5LP) for ECG signals? ECG signal is fast, period is about 1sec, and the frequencies are from 0.05 up to 150Hz. Is the sampling speed of 20 bit ADC (max 187 sps) the biggest problem? Signals from the electrodes are sent to IA (using two PGAs, gain = 2) , then I send signals to ADC, and after that to Filter component (LPF 150Hz). I need big resolution because ECG signal is 0.1-5mV. So I need your help, opinions and suggestions.
Hello.
I have a problem to read IO pin status.
Device:CY8C5868AXI-LP035
Pin name:OK_MPU, Port:12[3] ,Type:Digital Input,
Drive mode:Strong drive (to connect to other output enable pins)
Then I write in the program
tmp = OK_MPU_Read();
But if OK_MPU pin is connected to GND, Always tmp status = "1".
How can I read correct pin status ?
Please give advice to me.
hi friends
I want to access a reg type variable in Verilog. Normally I can send data to verilog with CY_SET_REG8 command.
for example CY_SET_REG8(ParalelToSerial_1_MyTxReg__CONTROL_REG,0x81);
So How is the Verilog variable sent to the C side?
I've been looking at the forums and tried multiple examples Importing a CyComponentLibrary, to be able to add code which doesn't get removed each time by the default library when I build. And no, the available areas to add code are not on the places I need. So I need to overide the standard library component.
I found a Cypress Tutorial video that shows how to import, but then I get many errors of double references. That video also shows that these components get added in a MyComponents in the Component catalog, which I assume is a tutorial from an old version of creator. As I only get Yellow errors in the added component in the Cypress Component catalog.
I then found an other tutorial that renames the imported component and updates all the namespaces in each of the component files. to avaoid double references. I did this, but 2 errors I can't solve:
M0123: The type or namespace name 'ArrayEditor" does not exists in the namespace 'SystemComponentModel.Design' in cycdc,cs and cyaudio2_0.cs from the USBFS component.
Can anyone help me how to properly import a component from the library. It should be something simple no? I understand why, but it's very annoying it updates automatically the components. There should be just an auto on/off setting on each component for advanced programming.
1. I built a bootloader project with dual APP.After complie it I found there are too many differents between two app zones from bootloadable.hex file. Why this happen?
2. I set bootloadable address is 0x8000 and compile dual bootloadable project. App start address is 0x8011 from metadata byte 1-4 in .hex file. why it is a odd number but not 0x8000 or 0x8010.
3. How to realize there is no reset switch between Bootloader and bootloadable? No both hardware reset and registers are cleared.After switch from bootloader to bootloadable, some funtion became abnormal. Even if I add routine reset() manually follow on main().Only valid method is use routine CySoftWareReset().
In attached project, there are ADC and UART component. To test it, I used the potentiometer and then I plotted its values in MATLAB in real-time. The project works fine. Now I want to add Filter component (1 channel, LPF) between ADC and UART, because I'll bring AC signal to the input of the ADC. I know that ADC can send data to Filter using DMA (there are example projects about that). The problem is that I don't know how to trasfer data from Filter to UART? And is it still posible to plot the signal in real time?
Thank you in advance.
Hello.Some examples of using an external rtc with I2C ?.
The RTC is DS1307.
Psoc 5lp CY8C5888LTI-LP097
Please teach me how to transmit data to external 16 bit D/AC (AD5696, Analog Devices) by using I2C master in PSoC 5LP. I programmed C firmware refer to Sample Code "DelSig_I2CM" in PSoC creator, not only D/AC didn't work , but also SDA and SCL signal have been seen using oscilloscope.
-------------------------------------------------------------------------------------------
/* Parameters used:
* I2C Master
* Implementation Fixed function
* Data rate 400kbps
* SDA SCL pin config Open drain, drives low
* Pull-up resistors 1.8kΩ each
*
* Delta Sigma ADC
* Resolution 12 bits
* Conversion Rate 1000000 SPS
* Input mode Single ended
*/
#include <project.h>
#define I2C_SLAVE_ADDRESS (12u)
#define WR_BUFFER_SIZE (2u)
uint8 X_IN = 0u;
uint8 temp = 0u;
uint8 sample_segment[WR_BUFFER_SIZE];
uint16 result[3] = {0u};
int main(void)
{
ADC_SAR_IN_Start();
ADC_SAR_IN_StartConvert();
I2CM_Start();
CyGlobalIntEnable;
for(;;)
{
ADC_SAR_IN_IsEndConversion(ADC_SAR_IN_WAIT_FOR_RESULT);
result[X_IN] = ADC_SAR_IN_GetResult16();
sample_segment[0] = result[X_IN] >> 8u & 0x00FFu;
sample_segment[1] = result[X_IN] & 0x00FFu;
do
{
temp = I2CM_MasterWriteBuf(I2C_SLAVE_ADDRESS, (uint8 *)sample_segment, WR_BUFFER_SIZE, I2CM_MODE_COMPLETE_XFER);
}
while(temp != I2CM_MSTR_NO_ERROR);
while(I2CM_MasterStatus() & I2CM_MSTAT_XFER_INP);
temp = I2CM_MasterClearStatus();
}
}
Looks like I have a 'ghost' wire in my project. Normally when the schematic has an identical error on a wire, it does not finalize the build.
The strange thing here is that the project builds and works fine, and when trying to find the error in the schematic it does not highlight 'red' when I double click the error.
I tried removing all wires, drew a box around the area, and deleted that area. Made the connections again, but still that fake wire lives somewhere in the project.
Is there a more advanced way to lookup where that fake wire should be?
Hello,
I just got last week my CY8CKIT-059 PSoC® 5LP Prototyping Kit and since then I've been busy with the very steep learning curve.
Testing things, I've created few designs (projects) of my own and now my questions are:
Thank you.
